RLE on the OLS

When I started playing with the OpenBench Logic Sniffer (OLS), I came across the Run Length Encoding option in Jawi's SUMP client. The trouble was I couldn't get consistent results using it. Digging through the Dangerous Prototypes forum showed some issues with RLE using the v2 firmware. Forum user 'dogsbody' has made a huge contribution porting the FPGA HDL to Verilog. Fixing up various issues with the firmware. It looks like the v3 FPGA and PIC firmware is now addressing RLE issues. Links to v3 can be found here. Make sure to also grab at least v0.9.3 SP1 of Jawi's SUMP client.

Hopefully later I can repeat the previous posts testing, and see if RLE works and captures more that the ~450 micro-seconds of samples. Fingers crossed! And then, onto SPI sniffing...

From Project: Burt

UPDATE: I managed to update the OLS to v3 of the PIC and FPGA firmware. Repeating the test in the previous blog post, but using RLE compression, looks like it is a lot more stable now. As expected the compression captures more than 10x the number of samples, with this simple UART test.

Unfortunately it looks like the UART analysis plugin in Jawi's SUMP client hasn't been updated to cope with RLE. Sampling at 50MHz without RLE works great. But at the same sampling rate with RLE compression enabled, the UART analysis fails to properly decode the Tx data :(

As you can see from the picture I have also moved to using the GHI FEZ Domino to squirt out UART data. I have put a Visual C# solution up on my GoogleCode SVN repository that squirts data out of UART0.

Getting to grips with the OpenBench Logic Sniffer

I haven't used a Logic Analyzer since the mid-90s. With new products on the horizon, it's starting to become something needed with this hobby work. Budget constraints have always made it difficult to justify picking up a second hand analyzer. So I was intrigued to come across the OpenBench Login Sniffer (OLS). I ordered one from Proto-Pic, here in the UK. They delivered version 1.01 of the OLS board.

The first step was to make sure that the OLS was up-to-date with FPGA and PIC firmware. At the time of writing v2.12b of the OLS software is available here. Included is a simple application that can flash the OLS EEPROM with new FPGA bit-stream, and update the PIC firmware.

The Gadget Factory has a YouTube channel with a few videos showing FPGA logic analysis and UART debugging. Setting up some UART transmission looked like the easiest way to try out the OLS, and quick to setup on the Arduino Deumilanove.

The OLS is limited with the number of samples it can record, so we need to tell the OLS when we are about to transmit over a UART line. The Arduino runs with a 16 MHz crystal, so the OLS should be able to pick up a pulse on one of the digital I/O pins.

Below is the Wiring code to setup the UART on pins 2, and 3. Plus the trigger pulse output on pin 4. The NewSoftSerial library is used to allow for higher baud rates to be tested.

#include <newsoftserial.h>
NewSoftSerial UART1(2,3); // rx,tx
void setup()
    pinMode(4, OUTPUT);
    digitalWrite(4, LOW);
    UART1.begin(115200);
}
void loop()
    digitalWrite(4, HIGH);
    digitalWrite(4, LOW);
    UART1.print("hello");
}

This simple PDE file can be found here. Also at that SVN location is the project file used with the OLS alternative SUMP client (Jawi's version supplied with the v2.12b OLS software).

I connected the OLS breakout probes to Gnd on the Arduino, and the digital I/O pins 2, 3, and 4. With the above Wiring sketch uploaded to the Arduino I was then able to start getting to grips with Jawi's Java SUMP Client. I ended up sampling at 50 MHz, and that was able to capture just over 450 micro seconds worth of data. The SUMP Client has plugins for analyzing common bus protocols. Below is the UART analysis. As you can see, the OLS managed to capture the UART Tx from the Arduino, result!!

UART Analysis results

---

Generated: 27 February 2011

Statistics
Decoded bytes	5
Detected bus errors	0
Baudrate	230400 (exact: 122249)

		RxD				TxD
Index	Time	Hex	Bin	Dec	ASCII	Hex	Bin	Dec	ASCII
0	23.280 μs					0x68	0b01101000	104	h
1	112.040 μs					0x65	0b01100101	101	e
2	200.780 μs					0x6c	0b01101100	108	l
3	289.520 μs					0x6c	0b01101100	108	l
4	378.280 μs					0x6f	0b01101111	111	o

Next up SPI testing...