RLE on the OLS

When I started playing with the OpenBench Logic Sniffer (OLS), I came across the Run Length Encoding option in Jawi's SUMP client. The trouble was I couldn't get consistent results using it. Digging through the Dangerous Prototypes forum showed some issues with RLE using the v2 firmware. Forum user 'dogsbody' has made a huge contribution porting the FPGA HDL to Verilog. Fixing up various issues with the firmware. It looks like the v3 FPGA and PIC firmware is now addressing RLE issues. Links to v3 can be found here. Make sure to also grab at least v0.9.3 SP1 of Jawi's SUMP client.

Hopefully later I can repeat the previous posts testing, and see if RLE works and captures more that the ~450 micro-seconds of samples. Fingers crossed! And then, onto SPI sniffing...

From Project: Burt

UPDATE: I managed to update the OLS to v3 of the PIC and FPGA firmware. Repeating the test in the previous blog post, but using RLE compression, looks like it is a lot more stable now. As expected the compression captures more than 10x the number of samples, with this simple UART test.

Unfortunately it looks like the UART analysis plugin in Jawi's SUMP client hasn't been updated to cope with RLE. Sampling at 50MHz without RLE works great. But at the same sampling rate with RLE compression enabled, the UART analysis fails to properly decode the Tx data :(

As you can see from the picture I have also moved to using the GHI FEZ Domino to squirt out UART data. I have put a Visual C# solution up on my GoogleCode SVN repository that squirts data out of UART0.